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3.3 V, 15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
FEATURES
TIA/EIA RS-485/RS-422 compliant 15 kV ESD protection on RS-485 input/output pins Data rates ADM3070E/ADM3071E/ADM3072E: 250 kbps ADM3073E/ADM3074E/ADM3075E: 500 kbps ADM3076E/ADM3077E/ADM3078E: 16 Mbps Half- and full-duplex options True fail-safe receiver inputs Up to 256 nodes on the bus -40C to +125C temperature option Hot-swap input structure on DE and RE pins Reduced slew rates for low EMI Low power shutdown current (all except ADM3071E/ADM3074E/ADM3077E) Outputs high-Z when disabled or powered off Common-mode input range: -7 V to +12 V Thermal shutdown and short-circuit protection 8-lead and 14-lead narrow SOIC packages
FUNCTIONAL BLOCK DIAGRAMS
VCC
ADM3070E/ ADM3073E/ ADM3076E
RO RE DE DI D Z Y
06285-001
R
A
B
GND
Figure 1.
VCC
ADM3071E/ ADM3074E/ ADM3077E
RO R A
B
APPLICATIONS
Power/energy metering Industrial control Lighting systems Telecommunications Security systems Instrumentation
DI D Z Y
06285-002
GND
.
Figure 2.
VCC
GENERAL DESCRIPTION
The ADM3070E to ADM3078E are 3.3 V, low power data transceivers with 15 kV ESD protection suitable for full- and half-duplex communication on multipoint bus transmission lines. They are designed for balanced data transmission, and they comply with TIA/EIA standards RS-485 and RS-422. The devices have an unit load receiver input impedance, which allows up to 256 transceivers on a bus. Because only one driver should be enabled at any time, the output of a disabled or powered-down driver is tristated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which eliminates the need for external bias resistors and ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ceases.
RO RE DE DI
ADM3072E/ ADM3075E/ ADM3078E
R A B D
06285-003
GND
Figure 3.
(continued on Page 3)
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 4 Timing Specifications--ADM3070E/ADM3071E/ ADM3072E.................................................................................... 5 Timing Specifications--ADM3073E/ADM3074E/ ADM3075E.................................................................................... 6 Timing Specifications--ADM3076E/ADM3077E/ ADM3078E.................................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Test Circuits and Switching Characteristics................................ 10 Typical Performance Characteristics ........................................... 12 Circuit Description......................................................................... 15 Function Tables........................................................................... 15 Receiver Fail-Safe ....................................................................... 15 Hot-Swap Capability .................................................................. 16 Line Length vs. Data Rate ......................................................... 16 15 kV ESD Protection ............................................................. 16 Human Body Model .................................................................. 16 256 Transceivers on the Bus...................................................... 16 Reduced EMI and Reflections .................................................. 16 Low Power Shutdown Mode..................................................... 17 Driver Output Protection.......................................................... 17 Typical Applications................................................................... 17 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20
REVISION HISTORY
10/06--Rev. 0 to Rev. A Added ADM3077E and ADM3078E ...............................Universal Changes to Figure 2 and Figure 3................................................... 1 Changes to Figure 5 and Figure 6................................................... 9 Changes to Figure 34 and Figure 35............................................. 17 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 8/06--Revision 0: Initial Version
Rev. A | Page 2 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
GENERAL DESCRIPTION
(continued from Page 1) The driver outputs of the 250 kbps and 500 kbps devices are slew rate limited, in order to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. Table 1. Selection Table
Part No. ADM3070E ADM3071E ADM3072E ADM3073E ADM3074E ADM3075E ADM3076E ADM3077E ADM3078E Half/Full Duplex Full Full Half Full Full Half Full Full Half Data Rate (Mbps) 0.25 0.25 0.25 0.5 0.5 0.5 16 16 16 Slew Rate Limited Yes Yes Yes Yes Yes Yes No No No Driver/Receiver Enable Yes No Yes Yes No Yes Yes No Yes Low Power Shutdown Yes No Yes Yes No Yes Yes No Yes Nodes on Bus 256 256 256 256 256 256 256 256 256 15 kV ESD on Bus Pins Yes Yes Yes Yes Yes Yes Yes Yes Yes Pin Count 14 8 8 14 8 8 14 8 8
The parts are fully specified over the industrial temperature ranges and are available in 8-lead and 14-lead narrow SOIC packages.
Rev. A | Page 3 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
SPECIFICATIONS
VCC = 3.3 V 10%, TA = TMIN to TMAX, unless otherwise noted. Table 2. ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
Parameter DRIVER Differential Outputs Differential Output Voltage Symbol Min Typ Max Unit Test Conditions/Comments
VOD
2.0 1.5
|VOD| for Complementary Output States 1 Common-Mode Output Voltage |VOC| for Complementary Output States1 Short-Circuit Output Current Short-Circuit Foldback Output Current Output Leakage (Y, Z) Full Duplex Logic Inputs Input High Voltage Input Low Voltage Input Hysteresis Logic Input Current Input Impedance First Transition Thermal Shutdown Threshold Thermal Shutdown Hysteresis RECEIVER Differential Inputs Differential Input Threshold Voltage Input Hysteresis Input Resistance (A, B) Input Current (A, B) RO Logic Output Output High Voltage Output Low Voltage Short-Circuit Output Current Tristate Output Leakage Current POWER SUPPLY Supply Current
VOD VOC VOC IOSD IOSDF IO
VCC/2 40
-250
VCC VCC VCC 0.2 3 0.2 250
-40 -20
20 125
-100
V V V V V V mA mA mA mA A A V V mV A k C C
RL = 100 (RS-422) (see Figure 7) RL = 54 (RS-485) (see Figure 7) No load R = 54 or 100 (see Figure 7) R = 54 or 100 (see Figure 7) R = 54 or 100 (see Figure 7) 0 V < VOUT < 12 V -7 V < VOUT < VCC (VCC - 1 V) < VOUT < 12 V -7 V < VOUT < +1 V DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = -7 V DE, DI, RE DE, DI, RE DE, DI, RE DE, DI, RE DE
VIH VIL VHYS IIN1 TTS TTSH
2.0 0.8 100 1 175 15 1 10
VTH VTH RIN IA, B
-200
-125
-50
15 96 125
-100
mV mV k A A V V mA A mA mA mA A kV kV
-7 V < VCM < +12 V VA + VB = 0 V -7 V < VCM < +12 V DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V DE = 0 V, VCC = 0 V or 3.6 V, VIN = -7 V
VOH VOL IOSR IOZR ICC
VCC - 0.6 0.4 80 1 0.8 0.8 0.8 0.05 15 4 1.5 1.5 1.5 10
IOUT = -1 mA IOUT = 1 mA 0 V < VRO < VCC VCC = 3.6 V, 0 V < VOUT < VCC No load, DE = VCC, RE = 0 V No load, DE = VCC, RE = VCC No load, DE = 0 V, RE = 0 V DE = 0 V, RE = VCC Human body model Human body model
Shutdown Current ESD PROTECTION A, B, Y, Z Pins All Pins Except A, B, Y, Z Pins
1
ISHDN
|VOD| and |VOC| are the changes in VOD and VOC, respectively, when the DI input changes state.
Rev. A | Page 4 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TIMING SPECIFICATIONS--ADM3070E/ADM3071E/ADM3072E
VCC = 3.3 V 10%, TA = TMIN to TMAX, unless otherwise noted. Table 3.
Parameter DRIVER Maximum Data Rate Propagation Delay, Low to High Level Propagation Delay, High to Low Level Rise Time/Fall Time |tDPLH - tDPHL| Differential Driver Output Skew Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low RECEIVER Maximum Data Rate Propagation Delay, Low to High Level Propagation Delay, High to Low Level |tRPLH - tRPHL| Output Skew Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low TIME TO SHUTDOWN Symbol Min 250 250 250 350 Typ Max Unit kbps ns ns ns ns ns ns ns ns ns ns kbps ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
tDPLH tDPHL tDR/tDF tDSKEW tDZH tDZL tDLZ tDHZ tDZH(SHDN) tDZL(SHDN)
1500 1500 1600 200 2500 2500 100 100 5500 5500
CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) (See Figure 10) (See Figure 11) (See Figure 11) (See Figure 10) (See Figure 10) (See Figure 11)
250 tRPLH tRPHL tRSKEW tRZH tRZL tRLZ tRHZ tRZH(SHDN) tRZL(SHDN) tSHDN 200 200 30 50 50 50 50 4000 4000 600
CL = 15 pF (see Figure 12 and Figure 13) CL = 15 pF (see Figure 12 and Figure 13) CL = 15 pF (see Figure 12 and Figure 13) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14)
50
200
Rev. A | Page 5 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TIMING SPECIFICATIONS--ADM3073E/ADM3074E/ADM3075E
VCC = 3.3 V 10%, TA = TMIN to TMAX, unless otherwise noted. Table 4.
Parameter DRIVER Maximum Data Rate Propagation Delay, Low to High Level Propagation Delay, High to Low Level Rise Time/Fall Time |tDPLH - tDPHL| Differential Driver Output Skew Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low RECEIVER Maximum Data Rate Propagation Delay, Low to High Level Propagation Delay, High to Low Level |tRPLH - tRPHL| Output Skew Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low TIME TO SHUTDOWN Symbol Min 500 180 180 200 Typ Max Unit kbps ns ns ns ns ns ns ns ns ns ns kbps ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
tDPLH tDPHL tDR/tDF tDSKEW tDZH tDZL tDLZ tDHZ tDZH(SHDN) tDZL(SHDN)
800 800 800 100 2500 2500 100 100 4500 4500
CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) (See Figure 10) (See Figure 11) (See Figure 11) (See Figure 10) (See Figure 10) (See Figure 11)
500 tRPLH tRPHL tRSKEW tRZH tRZL tRLZ tRHZ tRZH(SHDN) tRZL(SHDN) tSHDN 200 200 30 50 50 50 50 4000 4000 600
CL = 15 pF (see Figure 12 and Figure 13) CL = 15 pF (see Figure 12 and Figure 13) CL = 15 pF (see Figure 12 and Figure 13) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14)
50
200
Rev. A | Page 6 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TIMING SPECIFICATIONS--ADM3076E/ADM3077E/ADM3078E
VCC = 3.3 V 10%, TA = TMIN to TMAX, unless otherwise noted. Table 5.
Parameter DRIVER Maximum Data Rate Propagation Delay, Low to High Level Propagation Delay, High to Low Level Rise Time/Fall Time |tDPLH - tDPHL| Differential Driver Output Skew Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low RECEIVER Maximum Data Rate Propagation Delay, Low to High Level Propagation Delay, High to Low Level |tRPLH - tRPHL| Output Skew Enable to Output High Enable to Output Low Disable Time from Low Disable Time from High Enable Time from Shutdown to High Enable Time from Shutdown to Low TIME TO SHUTDOWN Symbol Min 16 tDPLH tDPHL tDR/tDF tDSKEW tDZH tDZL tDLZ tDHZ tDZH(SHDN) tDZL(SHDN) 16 tRPLH tRPHL tRSKEW tRZH tRZL tRLZ tRHZ tRZH(SHDN) tRZL(SHDN) tSHDN 40 40 75 75 8 50 50 50 50 1800 1800 600 50 50 15 8 150 150 100 100 1800 1800 Typ Max Unit Mbps ns ns ns ns ns ns ns ns ns ns Mbps ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
1250 1250
CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) CL = 50 pF, RL = 54 (see Figure 8 and Figure 9) (See Figure 10) (See Figure 11) (See Figure 11) (See Figure 10) (See Figure 10) (See Figure 11)
CL = 15 pF (see Figure 12 and Figure 13) CL = 15 pF (see Figure 12 and Figure 13) CL = 15 pF (see Figure 12 and Figure 13) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14) (See Figure 14)
50
200
Rev. A | Page 7 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 6.
Parameter VCC to GND Digital Input/Output Voltage (DE, RE, DI) Receiver Output Voltage (RO) Driver Output (A, B, Y, Z)/Receiver Input (A, B) Voltage Driver Output Current Operating Temperature Range ADM307xEA_ ADM307xEY_ Storage Temperature Range JA Thermal Impedance 8-Lead SOIC_N 14-Lead SOIC_N Lead Temperature, Soldering (20 sec) Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to (VCC + 0.3 V) -8 V to +13 V 250 mA -40C to +85C -40C to +125C -65C to +150C 158C/W 120C/W 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. A | Page 8 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC 1 RO 2 RE 3 DE 4 DI 5 GND 6 GND 7 NC = NO CONNECT
14
VCC NC A B Z Y
06285-004
ADM3070E/ ADM3073E/ ADM3076E
TOP VIEW (Not to Scale)
13 12 11 10 9 8
VCC 1 RO 2 DI 3 GND 4
ADM3071E/ ADM3074E/ ADM3077E
TOP VIEW (Not to Scale)
8 7 6 5
A B
06285-005
RO 1 RE 2 DE 3 DI 4
Y
5
GND
Figure 4. ADM3070E/ADM3073E/ADM3076E Pin Configuration
Figure 5. ADM3071E/ADM3074E/ADM3077E Pin Configuration
Figure 6. ADM3072E/ADM3075E/ADM3078E Pin Configuration
Table 7. Pin Function Descriptions
ADM3070E/ ADM3073E/ ADM3076E Pin No. 2 3 ADM3071E/ ADM3074E/ ADM3077E Pin No. 2 N/A ADM3072E/ ADM3075E/ ADM3078E Pin No. 1 2
Mnemonic RO RE
4
N/A
3
DE
5
3
4
DI
6, 7 9 N/A 12 10 N/A 11 14 1, 8, 13
4 5 N/A 8 6 N/A 7 1 N/A
5 N/A 6 N/A N/A 7 N/A 8 N/A
GND Y A A Z B B VCC NC
Description Receiver Output. When enabled, if (A - B) -50 mV, RO is high. If (A - B) -200 mV, RO is low. Receiver Output Enable. A low level enables the receiver output. A high level places it in a high impedance state. If RE is high and DE is low, the device enters a low power shutdown mode. Driver Output Enable. A high level enables the driver differential A and B outputs. A low level places it in a high impedance state. If RE is high and DE is low, the device enters a low power shutdown mode. Driver Input. With a half-duplex part when the driver is enabled, a logic low on DI forces A low and B high; a logic high on DI forces A high and B low. With a full-duplex part when the driver is enabled, a logic low on DI forces Y low and Z high; a logic high on DI forces Y high and Z low. Ground. Noninverting Driver Output. Noninverting Receiver Input A and Noninverting Driver Output A. Noninverting Receiver Input A. Inverting Driver Output. Inverting Receiver Input B and Inverting Driver Output B. Inverting Receiver Input B. Power Supply, 3.3 V 10%. Bypass VCC to GND with a 0.1 F capacitor. No Connect. Not internally connected. Can be connected to GND.
Rev. A | Page 9 of 20
06285-006
NC
Z
ADM3072E/ ADM3075E/ ADM3078E
TOP VIEW (Not to Scale)
8 7 6
VCC B A
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
Y RL/2 VOD RL/2 Z
06285-007
VOC
VCC S1 0V OR 3V D + CL 50pF RL 500 OUT
Figure 7. Driver DC Test Load
3V DE Y DI Z VOD RL CL
06285-008
GENERATOR
50
Figure 8. Driver Timing Test Circuit
VCC DI 0V VCC/2
VCC DE
tDZL, tDZL(SHDN) tDLZ
VCC/2 0V
tDPLH
tDPHL
VCC
06285-011
1/2VO
OUT VOL
VOM = (VOL + VCC)/2 0.25V
Z VO Y 1/2VO +VO VDIFF 0V -VO VDIFF = V (Y) - V (Z) 90% 10% 90% 10%
06285-009
Figure 11. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN))
tDR
tDF
tDSKEW = |tDPLH - tDPHL |
B ATE VID A R
RECEIVER OUTPUT
06285-012
Figure 9. Driver Propagation Delays
S1 0V OR 3V D + CL 50pF OUT RL 500
Figure 12. Receiver Propagation Delay Test Circuit
GENERATOR
50
A
VCC DE VCC/2 0V 0.25V VOH OUT VOM = (0 + VOH)/2 0V
06285-010
+1V -1V
B
tDZH, tDZH(SHDN)
tRPLH
VOH RO VOL 1.5V
tRPHL
NOTES 1. THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns.
tDHZ
Figure 10. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN))
Figure 13. Receiver Propagation Delays
Rev. A | Page 10 of 20
06285-013
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
+1.5V -1.5V S3 VID 1k + CL 15pF S2 S1 VCC
GENERATOR
50
S1 OPEN S2 CLOSED S3 = +1.5V RE
3V RE 0V
S1 CLOSED S2 OPEN S3 = -1.5V 1.5V
3V
0V
tRZL, tRZL(SHDN) tRZH, tRZH(SHDN)
RO VOH VOH/2 0V RO VCC (VOL + VCC)/2 VOL
S1 OPEN S2 CLOSED S3 = +1.5V RE 1.5V
3V RE 0V
S1 CLOSED S2 OPEN S3 = -1.5V 1.5V
3V
tRHZ
VOH RO
tRLZ
0V
VCC RO
06285-014
0.25V
0V
VOL
0.25V
Figure 14. Receiver Enable and Disable Times
Rev. A | Page 11 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TYPICAL PERFORMANCE CHARACTERISTICS
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -40 3.30 IRO = -1mA 3.25
OUTPUT HIGH VOLTAGE (V)
06285-020
SUPPLY CURRENT (mA)
3.20
3.15
3.10
3.05
-10
20
50
80
110
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 15. Supply Current vs. Temperature
-18 -16
Figure 18. Receiver Output High Voltage vs. Temperature
0.7 0.6 IRO = 1mA
OUTPUT LOW VOLTAGE (V)
-14
OUTPUT CURRENT (mA)
0.5 0.4 0.3 0.2 0.1 0 -50
-12 -10 -8 -6 -4 -2
06285-021
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-25
0
25
50
75
100
125
OUTPUT HIGH VOLTAGE (V)
TEMPERATURE (C)
Figure 16. Output Current vs. Receiver Output High Voltage
25
Figure 19. Receiver Output Low Voltage vs. Temperature
100 90
20
80
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
70 60 50 40 30 20 10
15
10
5
06285-022
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT LOW VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 17. Output Current vs. Receiver Output Low Voltage
Figure 20. Driver Output Current vs. Differential Output Voltage
Rev. A | Page 12 of 20
06285-025
0
0
06285-024
0
06285-023
3.00 -50
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
2.6 RL = 54 0.9 0.8
DIFFERENTIAL OUTPUT VOLTAGE (V)
2.5
2.3 2.2 2.1 2.0 1.9 1.8 1.7
06285-026
SHUTDOWN CURRENT (A)
2.4
0.7 0.6 0.5 0.4 0.3 0.2 0.1
06285-029 06285-031 06285-030
1.6 -50
-25
0
25
50
75
100
125
0 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 21. Driver Differential Output Voltage vs. Temperature
120 1200
Figure 24. Shutdown Current vs. Temperature
100
1000
PROPAGATION DELAY (ns)
OUTPUT CURRENT (mA)
80
800
tDPHL tDPLH
60
600
40
400
20
200
-6
-5
-4
-3
-2
-1
0
1
2
3
4
06285-027
0 -7
0
-40
25 TEMPERATURE (C)
125
OUTPUT HIGH VOLTAGE (V)
Figure 22. Output Current vs. Driver Output High Voltage
120 700 600
Figure 25. ADM3070E/ADM3071E/ADM3072E Driver Propagation Delay vs. Temperature (250 kbps)
100
PROPAGATION DELAY (ns)
tDPHL
500 400 300 200 100 0
OUTPUT CURRENT (mA)
80
tDPLH
60
40
20
0
2
4
6
8
10
12
06285-028
0
-40
25 TEMPERATURE (C)
125
OUTPUT LOW VOLTAGE (V)
Figure 23. Output Current vs. Driver Output Low Voltage
Figure 26. ADM3073E/ADM3074E/ADM3075E Driver Propagation Delay vs. Temperature (500 kbps)
Rev. A | Page 13 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
35
tDPLH
30
tDPHL
3
DI
PROPAGATION DELAY (ns)
25 20 15 10 5 0 -50
M1 VY - VZ
-25
0
25
50
75
100
125
06285-032
TEMPERATURE (C)
CH3 2.0V M400s 125MS/s MATH1 2.01V 400ns
8ns/pt
A CH2
1.24V
Figure 27. ADM3076E/ADM3077E/ADM3078E Driver Propagation Delay vs. Temperature (16 Mbps)
70 60
Figure 30. ADM3073E/ADM3074E/ADM3075E Driver Propagation Delay (500 kbps)
tDPLH tDPHL
M1 VY - VZ
PROPAGATION DELAY (ns)
50 40 30 20 10 0 -50
-25
0
25
50
75
100
125
06285-033
TEMPERATURE (C)
CH3 2.0V MATH1 1.0V
M20ns 1.25GS/s 20ns
IT 400ps/pt A CH3
1.64V
Figure 28. Receiver Propagation Delay vs. Temperature
Figure 31. ADM3076E/ADM3077E/ADM3078E Driver Propagation Delay (16 Mbps)
DI
3
VA - VB M1 M1 VY - VZ RO
06285-034 06285-035
CH3 2.0V M1.0s 50MS/s MATH1 2.01V 1.0s
20ns/pt
A CH2
1.24V
3
Figure 29. ADM3070E/ADM3071E/ADM3072E Driver Propagation Delay (250 kbps)
CH3 2.0V M200ns 250MS/s MATH1 2.01V 200ns
4ns/pt
A CH2
1.24V
Figure 32. Receiver Propagation Delay
Rev. A | Page 14 of 20
06285-037
3
DI
06285-036
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
CIRCUIT DESCRIPTION
The ADM307xE series are high speed transceivers for RS485 and RS-422 communications. Each device contains one driver and one receiver. All devices feature fail-safe circuitry, which guarantees a logic high receiver output when the receiver inputs are open or shorted or when they are connected to a terminated transmission line with all drivers disabled (see the Receiver FailSafe section). The ADM307xE also feature a hot-swap capability, allowing line insertion without erroneous data transfer (see the Hot-Swap Capability section). The ADM3070E/ ADM3071E/ADM3072E feature reduced slew rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing for error-free data transmission at rates up to 250 kbps. The ADM3073E/ADM3074E/ADM3075E also offer slew rate limits, allowing transmit speeds up to 500 kbps. The ADM3076E/ ADM3077E/ADM3078E driver slew rates are not limited, making possible transmit speeds of up to 16 Mbps. The ADM3072E/ADM3075E/ADM3078E are half-duplex transceivers; the ADM3070E/ADM3071E/ADM3073E/ADM3074E/ ADM3076E/ADM3077E are each full-duplex transceivers. All devices operate from a single 3.3 V supply. Drivers are output short-circuit current limited, and thermal shutdown circuitry protects drivers against excessive power dissipation. When activated, the thermal shutdown circuitry places the driver outputs into a high impedance state.
ADM3071E/ADM3074E/ADM3077E
Table 10. Transmitting Truth Table
Transmitting Input DI 1 0 Y 1 0 Transmitting Outputs Z 0 1
Table 11. Receiving Truth Table
Receiving Input A-B -50 mV -200 mV Open/shorted Receiving Output RO 1 0 1
ADM3072E/ADM3075E/ADM3078E
Table 12. Transmitting Truth Table
RE X1 X1 0 1
1 2
Transmitting Inputs DE DI 1 1 1 0 0 X1 0 X1
Transmitting Outputs A, Y B, Z 1 0 0 1 High-Z2 High-Z2 Shutdown Shutdown
X = don't care. High-Z = high impedance.
FUNCTION TABLES
ADM3070E/ADM3073E/ADM3076E
Table 8. Transmitting Truth Table
RE X1 X1 0 1
1 2
Table 13. Receiving Truth Table
RE Transmitting Outputs Y Z 1 0 High-Z2 Shutdown 0 1 High-Z2 Shutdown 0 0 0 1 1
1 2
Transmitting Inputs DE DI 1 1 0 0 1 0 X1 X1
Receiving Inputs DE A-B 0 -50 mV 0 -200 mV 0 Open/shorted 1 X1 0 X1
Receiving Output RO 1 0 1 High-Z2 Shutdown
X = don't care. High-Z = high impedance.
X = don't care. High-Z = high impedance.
RECEIVER FAIL-SAFE
The ADM307xE family guarantees a logic high receiver output when the receiver inputs are shorted, open, or connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver input threshold between -50 mV and -200 mV. If the differential receiver input voltage (A - B) is greater than or equal to -50 mV, RO is logic high. If A - B is less than or equal to -200 mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver differential input voltage is pulled to 0 V by the termination. With the receiver thresholds of the ADM307xE family, this results in a logic high with a 50 mV minimum noise margin.
Table 9. Receiving Truth Table
RE 0 0 0 1 1
1 2
Receiving Inputs DE X1 X1 X1 1 0
A-B
Receiving Outputs RO 1 0 1 High-Z2 Shutdown
-50 mV -200 mV Open/shorted X1 X1
X = don't care. High-Z = high impedance.
Rev. A | Page 15 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
HOT-SWAP CAPABILITY (ALL EXCEPT ADM3071E/ADM3074E/ADM3077E)
Hot-Swap Inputs
When a circuit board is inserted into a hot, or powered, backplane, differential disturbances to the data bus can lead to data errors. During this period, processor logic output drivers are high impedance and are unable to drive the DE and RE inputs of the RS-485 transceivers to a defined logic level. Leakage currents up to 10 A from the high impedance state of the processor logic drivers can cause standard CMOS enable inputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance can cause coupling of VCC or GND to the enable inputs. Without the hotswap capability, these factors can improperly enable the driver or receiver of the transceiver. When VCC rises, an internal pulldown circuit holds DE low and RE high. After the initial powerup sequence, the pull-down circuit becomes transparent, resetting the hot-swap tolerable input. carried out while device power is applied. This type of testing is more representative of a real-world input/output discharge, which occurs when equipment is operating normally. The transmitter outputs and receiver inputs of the ADM307xE family are characterized for protection to a 15 kV limit using the human body model.
HUMAN BODY MODEL
Figure 33 shows the human body model and the current waveform it generates when discharged into a low impedance. This model consists of a 100 pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5 k resistor.
HIGH VOLTAGE GENERATOR R1 R2 DEVICE UNDER TEST
C1
ESD TEST METHOD HUMAN BODY MODEL ESD ASSOC. STD 55.1
R2 1.5k
C1 100pF
LINE LENGTH VS. DATA RATE
The RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, Figure 37 illustrates an example line repeater.
100% 90%
15 kV ESD PROTECTION
Two coupling methods are used for ESD testing: contact discharge and air-gap discharge. Contact discharge calls for a direct connection to the unit being tested. Air-gap discharge uses a higher test voltage but does not make direct contact with the test unit. With air-gap discharge, the discharge gun is moved toward the unit under test, developing an arc across the air gap, therefore the term air-gap discharge. This method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. The contact discharge method, while less realistic, is more repeatable and is gaining acceptance and preference over the air-gap method. Although very little energy is contained within an ESD pulse, the extremely fast rise time, coupled with high voltages, can cause failures in unprotected semiconductors. Catastrophic destruction can occur immediately as a result of arcing or heating. Even if catastrophic failure does not occur immediately, the device can suffer from parametric degradation that can result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure. Input/output lines are particularly vulnerable to ESD damage. Simply touching or connecting an input/output cable can result in a static discharge that damages or completely destroys the interface product connected to the input/output port. It is extremely important, therefore, to have high levels of ESD protection on the input/output lines. The ESD discharge can induce latch-up in the device under test, so it is important that ESD testing on the input/output pins be
IPEAK
36.8%
10%
tRL
tDL
TIME t
Figure 33. Human Body Model and Current Waveform
256 TRANSCEIVERS ON THE BUS
The standard RS-485 receiver input impedance is 12 k (1 unit load), and the standard driver can drive up to 32 unit loads. The ADM307xE family of transceivers has an unit load receiver input impedance (96 k), allowing up to 256 transceivers to be connected in parallel on one communication line. Any combination of these devices and other RS-485 transceivers with a total of 32 unit loads or fewer can be connected to the line.
REDUCED EMI AND REFLECTIONS
The ADM3070E/ADM3071E/ADM3072E feature reduced slew rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing for error-free data transmission at rates up to 250 kbps. The ADM3073E/ ADM3074E/ADM3075E offer higher driver output slew rate limits, allowing for transmit speeds of up to 500 kbps.
Rev. A | Page 16 of 20
06285-015
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
LOW POWER SHUTDOWN MODE (ALL EXCEPT ADM3071E/ADM3074E/ADM3077E)
Low power shutdown mode is initiated by bringing both RE high and DE low. In shutdown mode, the device draws less than 1 A of supply current. RE and DE can be driven simultaneously, but the parts are guaranteed not to enter shutdown if RE is high and DE is low for fewer than 50 ns. If the inputs are in this state for 600 ns or more, the parts are guaranteed to enter shutdown. Enable times tZH and tZL assume the part was not originally in a low power shutdown state (see the Test Circuits and Switching Characteristics section). Enable times tZH(SHDN) and tZL(SHDN) assume the part was originally shut down. It takes drivers and receivers longer to become enabled from low power shutdown mode (tZH(SHDN), tZL(SHDN)) than from driver/receiver disable mode (tZH, tZL). or by bus contention. Current limit protection on the output stage provides immediate protection against short circuits over the whole common-mode voltage range (see Figure 12 and Figure 13). In addition, a thermal shutdown circuit forces the driver outputs into a high impedance state if the die temperature rises excessively.
TYPICAL APPLICATIONS
The ADM3072E/ADM3075E/ADM3078E transceivers are designed for bidirectional data communications on multipoint bus transmission lines. Figure 34 shows a typical network applications circuit. The ADM3071E/ADM3074E/ADM3077E transceivers are designed for point-to-point transmission lines (see Figure 35). The ADM3070E/ADM3073E/ADM3076E transceivers are designed for full-duplex RS-485 networks (see Figure 36). To minimize reflections, terminate the line at both ends with a termination resistor (the value of the termination resistor should be equal to the characteristic impedance of the cable used) and keep stub lengths off the main line as short as possible.
DRIVER OUTPUT PROTECTION
The ADM307xE family features two methods to prevent excessive output current and power dissipation caused by faults
ADM3072E/ ADM3075E/ ADM3078E
RO RE DE DI D B B R A RT RT A
ADM3072E/ ADM3075E/ ADM3078E
R RO RE DE D DI
A
B
A
B
ADM3072E/ ADM3075E/ ADM3078E
R D R D
ADM3072E/ ADM3075E/ ADM3078E
RO
RE
DE
DI
RO
RE
DE
DI
06285-016
NOTES 1. MAXIMUM NUMBER OF NODES: 256. 2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
Figure 34. ADM3072E/ADM3075E/ADM3078E Typical Half-Duplex RS-485 Network
MASTER SLAVE
ADM3071E/ ADM3074E/ ADM3077E
RO R
A B Z
Y Z B A
ADM3071E/ ADM3074E/ ADM3077E
D DI
Y
Figure 35. ADM3071E/ADM3074E/ADM3077E Full-Duplex Point-to-Point Applications
Rev. A | Page 17 of 20
06285-017
DI
D
R
RO
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
MASTER SLAVE
ADM3070E/ ADM3073E/ ADM3076E
RO RE DE DI D R
A B RT
Y Z
ADM3070E/ ADM3073E/ ADM3076E
D
DE DI
Z Y RT
B A R RO RE
SLAVE
A
B
Z
Y
A
B
Z
Y
SLAVE
ADM3070E/ ADM3073E/ ADM3076E
R
D
R
D
ADM3070E/ ADM3073E/ ADM3076E
06285-019
RO RE DE
DI
RO
RE DE
DI
NOTES 1. MAXIMUM NUMBER OF NODES: 32. 2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
Figure 36. ADM3070E/ADM3073E/ADM3076E Full-Duplex RS-485 Network
ADM3070E/ ADM3073E/ ADM3076E
RO RE DE DI D R
A B RT DATA IN
Z Y RT DATA OUT
Figure 37. Line Repeater for ADM3070E/ADM3073E/ADM3076E
Rev. A | Page 18 of 20
06285-018
NOTES 1. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 1 5 4
4.00 (0.1574) 3.80 (0.1497)
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
8.75 (0.3445) 8.55 (0.3366)
14 1 8 7
4.00 (0.1575) 3.80 (0.1496)
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
1.75 (0.0689) 1.35 (0.0531) SEATING PLANE
0.50 (0.0197) 0.25 (0.0098) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060506-A
Figure 39. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches)
Rev. A | Page 19 of 20
060606-A
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
ORDERING GUIDE
Model ADM3070EARZ 1 ADM3070EARZ-REEL71 ADM3070EYRZ1 ADM3070EYRZ-REEL71 ADM3071EARZ1 ADM3071EARZ-REEL71 ADM3071EYRZ1 ADM3071EYRZ-REEL71 ADM3072EARZ1 ADM3072EARZ-REEL71 ADM3072EYRZ1 ADM3072EYRZ-REEL71 ADM3073EARZ1 ADM3073EARZ-REEL71 ADM3073EYRZ1 ADM3073EYRZ-REEL71 ADM3074EARZ1 ADM3074EARZ-REEL71 ADM3074EYRZ1 ADM3074EYRZ-REEL71 ADM3075EARZ1 ADM3075EARZ-REEL71 ADM3075EYRZ1 ADM3075EYRZ-REEL71 ADM3076EARZ1 ADM3076EARZ-REEL71 ADM3076EYRZ1 ADM3076EYRZ-REEL71 ADM3077EARZ1 ADM3077EARZ-REEL71 ADM3077EYRZ1 ADM3077EYRZ-REEL71 ADM3078EARZ1 ADM3078EARZ-REEL71 ADM3078EYRZ1 ADM3078EYRZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C
Package Description 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N)
Package Option R-14 R-14 R-14 R-14 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-14 R-14 R-14 R-14 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-14 R-14 R-14 R-14 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8
Ordering Quantity 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06285-0-10/06(A)
Rev. A | Page 20 of 20

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